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IDT7381 16-BIT CASCADABLE ALU
COMMERCIAL TEMPERATURE RANGE
16-BIT CMOS CASCADABLE ALU
FEATURES:
- - - - - - - - - - - - - High-performance 16-bit Arithmetic Logic Unit (ALU) 25ns to 55ns clocked ALU operations Ideal for radar, sonar or image processing applications 74S381 instruction set (8 functions) Replaces Gould S614381 or Logic Devices L4C381 Cascadable with or without carry look-ahead Pipeline or flow-through modes Internal feedback path for accumulation Three-state outputs TTL-compatible Produced with advanced submicron CMOS technology Available in PLCC Speeds available: L/25/30/40/55
IDT7381
DESCRIPTION:
The IDT7381 is a high-speed cascadable Arithmetic Logic Unit (ALU). These three-bus devices have two input registers, an ultra-fast 16-bit ALU and 16-bit output register. With IDT's high-performance CMOS technology, the IDT7381 can do arithmetic or logic operations in 25ns. The IDT7381 functionally replaces four 54/74S381 four-bit ALUs in a 68-pin package. The two input operands, A and B, can be clocked or fed through for flexible pipelining. The F output can also be set into clocked or flow-through mode. An output enable is provided for three-state control of the output port on a bus. The IDT7381 has three function pins to select 1 of 8 arithmetic or logic operations. The two R and S selection pins determine whether A, B, F or 0 are fed into the ALU. This ALU has carry-out, propagate and generate outputs for cascading using carry look-ahead.
FUNCTIONAL BLOCK DIAGRAM
A0 - 15 16 B0 - 1 5 16
ENA
A R EG
B R EG
CL K ENB
A MUX 0000 H R MUX 0000 H
B MUX
FT AB
S MUX 2
RS0
-1
P G C16 OVF Z
I 16-BIT AL U 3
0-2
C0
EN F
F RE G
FTF
F M UX PO W E R SU P P LY 16 F0 - 15 GND VCC
OE
COMMERCIAL TEMPERATURE RANGE
1
c 2001 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
APRIL 2001
DSC-2525/-
IDT7381 16-BIT CASCADABLE ALU
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
B14 B15 B13 B12 B11 A8 A7 A3 A5 A4 A1 B10 A2 A0 B9 A6 B8
A9 A10 A11 A12 A13 A14 A15 CL K VCC GND C16
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
8
7
6
5
4
3
1 68 67 66 65 64 63 62 61 60 Pin 1 59 Desig nato r 58 57 56 55 54 53 52 J68 - 1 51 50 49 48 47 46 45
2
B7 B6 B5 B4 B3 B2 B1 B0 ENA ENB FT AB RS 1 RS 0 I I I
2 1 0
P G
Z O VF EN F FTF
44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
F15 F11 F5 F13 F14 F12 F10 F9 F1 F8 F7 F6 F4 F3 F2 F0
C0
OE
PLCC TOP VIEW
2
IDT7381 16-BIT CASCADABLE ALU
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name A0 - A15 B0 - B15 ENA ENB FTAB
F0 - F15
I/O I I I I I
O
Description Sixteen-bit data input port. Sixteen-bit data input port. Register enable for the A input port; active low pin. Register enable for the B input port; active low pin. Flow-through control pin. When this pin is high, both register A and B are transparent. Sixteen-bit data output port. Register enable for the F output port; active low pin. Flow-through control pin. When this pin is high, the F register is transparent. Clock input. Output enable control pin. When this pin is high, the output port F is in a high impedance state. When low, the output port F is active. Carry input. This pin receives arithmetic carries from less significant ALU components in a cascade configuration. Carry output. This pin produces arithmetic carries to more significant ALU components in a cascaded configuration. This pin indicates a two's complement arithmetic overflow, when high. This pin indicates a zero output result, when high. Two control pins used to select input operands for the R and S multiplexers. Three control pins to select the ALU function performed. Indicates the carry propagate output state to the ALU. Indicates the carry generate output state to the ALU. Power supply pin, 5V. Ground pin, 0V.
ENF FTF CLK OE C0 C16 OVF Z RS0 - RS1 I0 - I2 P G VCC GND
I I I
I
I O O O I I O O
R AND S MUX TABLE
RS1 0 0 1 1 RS0 0 1 0 1 R Mux A A 0 A S Mux F 0 B B
ALU FUNCTION TABLE
I2 0 0 0 0 1 1 1 1 I1 0 0 1 1 0 0 1 1 I0 0 1 0 1 0 1 0 1 F=0 F = R + S + C0 F = R + S + C0 F = R + S + C0 F = R xor S F = R or S F = R and S F = all 1's Function
3
IDT7381 16-BIT CASCADABLE ALU
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM VCC TSTG IOUT Description Terminal Voltage with Respect to Ground Power Supply Voltage Storage Temperature DC Output Current Max. -0.5 to VCC + 0.5 -0.5 to +7.0 -55 to +125 50 Unit V V C mA
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Pkg. PGA PLCC PGA PLCC Typ. 10 5 12 7 pF Unit pF
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Under no circumstances should an input of an I/O Pin be greater than VCC + 0.5V.
NOTE: 1. This parameter is sampled at initial characterization and is not production tested.
DC ELECTRICAL CHARACTERISTICS
Commercial: TA = 0C to +70C, VCC = 5.0V 5%
Symbol VIH VIL IIH IIL IOS
(3)
Parameter Input HIGH Level Input LOW Level Input HIGH Current Input LOW Current Short Circuit Current Off State (High Impedance) Output Current Output HIGH Voltage Output LOW Voltage
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max., VIN = 2.7V VCC = Max., VIN = 0.5V VCC = Max., VOUT = GND VCC = Max. VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL VO = 0.5V VO = 2.7V IOH = -4mA IOL = 8mA
Min. 2 -- -- -- -20 -- -- 2.4 --
Typ.(2) -- -- -- -- -- -0.1 -0.1 -- --
Max. -- 0.8 10 -10 -100 -20 20 -- 0.5
Unit V V A A mA A V V
IOZ VOH VOL
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
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IDT7381 16-BIT CASCADABLE ALU
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Commercial: TA = 0C to +70C, VCC = 5.0V 5%
Symbol ICC ICC(3) ICCD(4) Parameter Quiescent Power Supply Current Quiescent Power Supply Current TTL Input HIGH Dynamic Power Supply Current VCC = Max. VIN =GND or VCC VCC = Max. VIN = 3.4V VCC = Max. Outputs disabled VIN = GND or VCC Mode: FTAB = FTF = 1 VCC = Max. Outputs Disabled All Data Inputs Disabled fi = 10MHz, fCP = 10MHz 50% Duty Cycle VIL = GND, VIH = VCC Mode: FTAB = FTF = 1 VCC = Max. Outputs Enabled. (CL = 50pF) All Data Inputs Sw itching fi = 10MHz, fCP = 10MHz 50% Duty Cycle VIL = GND, VIH = VCC Mode: FTAB = FTF = 1 IC(7) Total Power Supply Current VCC = Max. VIN = GND or VCC All Data Inputs Switching fi = 10MHz, fCP = 10MHz 50% Duty Cycle Outputs Disabled Outputs Enabled -- -- 22 42 39 76 mA mA Test Conditions(1) Min. -- -- -- Typ.(2) 2 0.5 15 Max. 6 1 48 Unit mA mA/ input A/ MHz
ICCD1
Dynamic Power Supply Current
--
20
33
mA
ICCD2(6)
Dynamic Power Supply Current
--
40
60
mA
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived from ICCD1 for use in Total Power Supply calculations. 5. Total power supply current is calculated as follows: IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 6. This parameter is not production tested but is an indicator of the power dissipated with outputs loaded. 7. Values for these conditions are examples of the IC formula in note 5 above. These are guaranteed but not tested.
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IDT7381 16-BIT CASCADABLE ALU
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
Maximum Combinational Propagation Delays IDT7381L25 From Input FTAB = 0, FTF = 0 CLK C0 I0-2, RS0, RS1 FTAB = 0, FTF = 1 CLK C0 I0-2, RS0, RS1 FTAB = 1, FTF = 0 A0-A15, B0-B15 CLK C0 I0-2, RS0, RS1 FTAB = 1, FTF = 1 A0-A15, B0-B15 C0 I0-2, RS0, RS1 26 22 22 18 -- 22 25 16 22 -- 13 -- -- 18 -- -- 22 25 -- 16 22 27 22 22 22 -- 22 26 16 22 13 -- -- 22 -- 22 26 16 22 F0-15 P, G, N Z,OVF
(VCC = 5V 5%, TA = 0C to +70C)
IDT7381L30 C16 22 16 22 22 16 22 22 -- 16 22 22 16 22 F0-15 20 -- -- 33 28 28 -- 19 -- -- 32 28 28 P, G, N 28 -- 28 28 -- 28 24 -- -- 28 24 -- 28 Z,OVF 30 20 28 30 20 28 30 -- 20 28 30 20 28 C16 28 20 28 28 20 28 28 -- 20 28 28 20 28 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Maximum Combinational Propagation Delays IDT7381L40 From Input FTAB = 0, FTF = 0 CLK C0 I0-2, RS0, RS1 FTAB = 0, FTF = 1 CLK C0 I0-2, RS0, RS1 FTAB = 1, FTF = 0 A0-A15, B0-B15 CLK C0 I0-2, RS0, RS1 FTAB = 1, FTF = 1 A0-A15, B0-B15 C0 I0-2, RS0, RS1 40 30 40 30 -- 32 40 28 34 32 20 35 55 37 55 36 -- 42 46 34 42 37 22 42 ns ns ns -- 26 -- -- 30 -- -- 32 40 -- 28 34 32 -- 20 35 -- 32 -- -- 36 -- -- 42 46 -- 34 42 37 -- 22 42 ns ns ns ns 46 30 40 30 -- 32 44 28 34 32 20 35 56 37 55 38 -- 42 53 34 42 36 22 42 ns ns ns 26 -- -- 30 -- 32 44 28 34 32 20 35 32 -- -- 38 -- 42 53 34 42 36 22 42 ns ns ns F0-15 P, G, N Z,OVF C16 F0-15 P, G, N IDT7381L55 Z,OVF C16 Unit
NOTES: 1. Only for FTF = 0. 2. Minimum propagation delays are not production tested but guaranteed to be greater than or equal to 3ns.
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IDT7381 16-BIT CASCADABLE ALU
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
Minimum Set-up and Hold Times Relative to Clock (CLK) IDT7381L25 Input FTAB = 0, FTF = X A0-A15, B0-B15 C0 (1) I0-2, RS0, RS1 (1) ENA, ENB, ENF FTAB = 1, FTF = 0 A0-A15, B0-B15 C0 I0-2, RS0, RS1 ENF 16 16 24 6 0 0 0 0 25 16 29 6 6 16 24 6 0 0 0 0 6 16 29 6 Set-up Hold
(VCC = 5V 5%, TA = 0C to +70C) - (Cont'd.)
IDT7381L40 Set-up 6 16 32 6 28 16 32 6 Hold 0 0 0 0 0 0 0 0 IDT7381L55 Set-up 8 21 44 8 35 21 44 8 Hold 0 0 0 0 0 0 0 0 Unit ns ns ns ns ns ns ns ns
IDT7381L30 Set-up Hold 0 0 0 0 0 0 0 0
Minimum Clock Cycle Times and Pulse Widths Parameter Clock LOW Time Clock HIGH Time Clock Period Maximum Output Enable/Disable Times Parameter Enable Time Disable Time IDT7381L25 10 10 IDT7381L30 15 15 IDT7381L40 18 18 IDT7381L55 20 20 Unit ns ns IDT7381L25 6 6 20 IDT7381L30 8 8 25 IDT7381L40 10 10 34 IDT7381L55 14 14 43 Unit ns ns ns
NOTES: 1. Only for FTF = 0. 2. Minimum propagation delays are not production tested but guaranteed to be greater than or equal to 3ns.
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IDT7381 16-BIT CASCADABLE ALU
COMMERCIAL TEMPERATURE RANGE
WAVEFORMS FOR FTAB = 0, FTF = X
T1 CLK T2
Set-up A0- 15 DATA 1 B0- 15 Set-up C0 DATA 1 DATA 2 DATA 2
Hold DATA 3
Hold DATA 3
Set-up I0- 2, DATA 1 RS0- 1 DATA 2
Hold DATA 3
Set-up ENA, ENB ENF DATA 1 DATA 2
Hold DATA 3
OE Prop. 1 Enable F0- 15 (FTF = 0) Prop. 3 Prop. 2 Prop. 1 F0- 15 (FTF = 1) Prop. 2 Prop. 1 Enable Disable Result Result Disable
P, G
Prop. 2 Prop. 1 Z, OVF Prop. 2 Prop. 1 C16 Prop. 3 Prop. 3
Result
Result
Result
Prop. 1: Propagation delay with respect to the CLK. Prop. 2: Propagation delay with respect to I0- 2, RS0- 2. Prop. 3: Propagation delay with respect to C0.
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IDT7381 16-BIT CASCADABLE ALU
COMMERCIAL TEMPERATURE RANGE
WAVEFORMS FOR FTAB = 1, FTF = X
T1 CLK (FTF = 0) Set-up A0- 15 DATA 1 B0- 15 Set-up C0 DATA 1 DATA 2 Hold DATA 3 DATA 2 DATA 3 Hold T2
Set-up I0- 2, DATA 1 RS0- 1 Set-up ENF DATA 1 DATA 2 DATA 2
Hold DATA 3
Hold DATA 3
OE Prop. 1 Enable F0- 15 (FTF = 0) Prop. 4 Prop. 3 Prop. 2 Enable F0- 15 (FTF = 1) Prop. 2 Result Prop. 4 (For FTF = 1 only) Prop. 3 Prop. 4 (for FTF = 1 only) Disable Result Result Disable
P, G
Prop. 2
Z, OVF Prop. 4 (For FTF = 1 only) Prop. 3 Prop. 2 C16 Result
Result
Prop. Prop. Prop. Prop.
1: 2: 3: 4:
Propagation Propagation Propagation Propagation
delay delay delay delay
with with with with
respect respect respect respect
to to to to
the CLK. I0- 2, RS0- 2. C0. A, B.
9
IDT7381 16-BIT CASCADABLE ALU
COMMERCIAL TEMPERATURE RANGE
PROPAGATION DELAY CALCULATIONS FOR TWO IDT7381S
To Output From Input FTAB = 0, FTF = 0 CLK C0 I0 - 2, RS0 - 1 A0 - 15, B0 - 15 ENA, ENB,ENF FTAB = 0, FTF = 1 CLK C0 I0 - 2, RS0 - 1 A0 - 15, B0 - 15 ENA, ENB,ENF FTAB = 1, FTF = 0 CLK C0 I0 - 2, RS0 - 1 A0 - 15, B0 - 15 ENA, ENB,ENF FTAB = 0, FTF = 1 CLK C0 I0 - 2, RS0 - 1 A0 - 15, B0 - 15 ENA, ENB,ENF As in 16-bit case .... .... .... .... (Clk C16) + (C0 F0-15) (C0 C16) + (C0 F0-15) (I0-2, RS0-1 C16) + (C0 F0-15) .... .... As in 16-bit case .... .... .... .... Don't care condition (C0 C16) + (C0 F0-15) (I0-2, RS0-1 C16) + (C0 F0-15) (A0-15, B0-15 C16) + (C0 F0-15) .... F0 - 15 Flags (1) (Clk C16) + (C0 flag) (C0 C16) + (C0 flag) (I0-2, RS0-1 C16) + (C0 flag) .... .... (Clk C16) + (C0 flag) (C0 C16) + (C0 flag) (I0-2, RS0-1 C16) + (C0 flag) .... .... .... (C0 C16) + (C0 flag) (I0-2, RS0-1 C16) + (C0 flag) (A0-15, B0-15 C16) + (C0 flag) .... Don't care condition (C0 C16) + (C0 flag) (I0-2, RS0-1 C16) + (C0 flag) (A0-15, B0-15 C16) + (C0 flag) .... To Set PUT Time Relative to Clock (CLK) .... (C0 C16) + (C0 set-up time) (I0-2, RS0-1 C16) + (C0 set-up time) As in 16-bit case As in 16-bit case .... (C0 C16) + (C0 set-up time) (I0-2, RS0-1 C16) + (C0 set-up time) As in 16-bit case As in 16-bit case .... (C0 C16) + (C0 set-up time) (I0-2, RS0-1 C16) + (C0 set-up time) As in 16-bit case As in 16-bit case .... .... .... .... ....
NOTE: 1. Flags are P, G, OVF, Z and C16.
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IDT7381 16-BIT CASCADABLE ALU
COMMERCIAL TEMPERATURE RANGE
CASCADING THE IDT7381
Some applications require 32-bit or wider input operands. Cascading is the hardware solution. It provides a high speed alternative in handling more than 16-bit wide operands. 1. Cascading the IDT7381 Cascading to 32-bit wide operands takes only two IDT7381s and no external hardware. However, cascading to data widths greater than 32bit can be done in two ways: without external hardware (slow method) or by using a carry look ahead generator. a) Cascading the IDT7381 without a carry-look-ahead generator: (Figures 1 and 2) 1. Connect the C16 output of the least significant device into the C0 input of the next most significant device. 2. Common lines to all devices are: RS0-1, I0-2, Clk, FTF, FTAB, ENA, ENB, ENF. 3. Take OVF, C16, P, G of the most significant device as valid. 4. The system's zero flag (Z) is obtained by ANDing all zero flag results. b) Cascading three or more IDT7381s with carry-look-ahead (CLA) generator: (Figure 3) 1. Connect the P and G outputs of each device to the CLA generator's corresponding inputs. 2. Take the CLA generator outputs into the C0 inputs of each device (except for the least significant one). 3. Common lines to all devices are: RS0-1, I0-2, Clk, FTF, FTAB, ENA, ENB, ENF. 4. Take OVF, C16, P, G of the most significant device as valid. 5. Carry-in to the system should be connected to the C0 input of the least significant device and also to the CLA generator. 2. Time Delay Considerations Once cascading has taken place, time delays may become critical in high performance systems. Our main interest here is focused on "propagation delays", i.e. calculating the time required for an input signal to propagate through several cascaded devices up to a specific output in another device within the cascaded system. Propagation Delay The propagation delay for two devices between the input and output of interest (input to output delay) is done as follows: 1. Calculate delay between the input and C16 in the first device. 2. Calculate delay between C0 and the output in the second device. 3. Add both results. The following table is an example on how to build a propagation delay table for all inputs in a 32-bit IDT7381 cascaded system. Propagation delay calculations can be extended to n-cascaded devices as the sum of the delays in all devices between the input and output of interest. That is: (Input)1 (C16)1 = t1 ... (C0)i (C16)i = ti (C0)i + 1 (C16)i + 1 = ti + 1
...
(C0)n (Output)n = tn Where the subscript i denotes the device number and the arrow () represents the delay in between. Notice that i + 1 is the immediate upper device from device i. Adding the delays ti we get: Propagation delay = t1 + t2 + ... + ti + ti + 1 + ... + tn Total Delay As seen from Figure 8, the propagation delay is within the IDT7381 devices only. A complete analysis should also include the delay associated with the transmission line Li (which depends on the line length and its impedance). This line delay should then be added to the propagation delay to obtain the total delay for the cascaded system: Total delay = Propagation delay + Transmission line delay
11
IDT7381 16-BIT CASCADABLE ALU
COMMERCIAL TEMPERATURE RANGE
A16 - 31
B16 - 31
A0 - 15
B0 - 15
G P
C16 OVF Z Z
M SD ID T7381
11 RS0 - 1
ID T7381
Clk, I
0 - 2,
ENA, ENB
ENF, FTF, FTAB C0 C16 C0 LSD Z CIN
F16 - 3 1
F0 - 15
Figure 1. Cascading Two IDT7381s to 32 Bits
A32 - 47
B32
- 47
A16 - 31
B16 - 31
A0 - 15
B0 - 15 RS0 - 1 Clk, I 0 - 2, ENA, ENB ENF, FTF, FTA B CIN
G P
C16 OVF Z
ID T7 381
ID T7381
ID T7381
11
C0 Z
M SD
C16 Z
C0
C16 C0 LS D Z
F32 - 4 7
F16 - 3 1
F0 - 15
Figure 2. Cascading Three IDT7381s to 48 Bits Wide without a Carry-lookahead Generator
A32 - 47
B32 - 47
A16
- 31
B16
- 31
A0 - 15
B0 - 15 RS0 - 1 Clk, I 0 - 2, ENA, ENB ENF, FTF, FTAB
G P
C16 OVF Z
ID T738 1
ID T738 1
ID T7 381
11
P G
C0 Z
MSD
P G
C0 Z
LS D
Z
C0
CIN
F32
- 47
F16 - 31
F0
- 15
C n+y
P1 G1
C n+x
P0 G0 Cn
FC T1 82/A Looka head G ene rator
Figure 3. Cascading Three IDT7381s to 48 Bits Wide with a Carry-lookahead Generator
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IDT7381 16-BIT CASCADABLE ALU
COMMERCIAL TEMPERATURE RANGE
A16 - 31 16
B16 - 31 16
A0 - 15 16 A Reg
B0 - 15 16 B Reg CLK
A Reg A M ux
B Reg
B M ux
A M ux
B M ux
R M ux
S M ux
R M ux
S M ux
16-Bit ALU C M SD
0
16-Bit ALU C16 LSD
F Reg
F Reg
F M ux
F M ux
16 F16 - 3 1
16 F0 - 15
Figure 4. 32-Bit Configuration for FTAB = 0, FTF = 0
A16 - 31 16 A R eg
B16 - 31 16 B Reg
A0 - 15 16 A Reg
B0 - 15 16 B Reg CLK
A M ux
B M ux
A M ux
B M ux
R M ux
S M ux
R M ux
S M ux
16-Bit ALU M SD C
0
16-Bit ALU C16 LSD
F M ux
F M ux
16 F16 - 3 1
16 F0 - 15
Figure 5. 32-Bit Configuration for FTAB = 0, FTF = 1
13
IDT7381 16-BIT CASCADABLE ALU
COMMERCIAL TEMPERATURE RANGE
A16 - 31 16
B16 - 31 16
A0 - 15 16
B0 - 15 16 CLK
A M ux
B M ux
A M ux
B M ux
R M ux
S M ux
R M ux
S M ux
16-Bit ALU C M SD
0
16-Bit ALU C16 LSD
F Reg
F Reg
F M ux
F M ux
16 F16 - 3 1
16 F0 - 15
Figure 6. 32-Bit Configuration for FTAB = 1, FTF = 0
A16 - 31 16
B16 - 31 16
A0 - 15 16
B0 - 15 16
A M ux
B M ux
A M ux
B M ux
R M ux
S M ux
R M ux
S M ux
16-Bit ALU C M SD
0
16-Bit ALU C16 LSD
F M ux
F M ux
16 F16 - 3 1
16 F0 - 15
Figure 7. 32-Bit Configuration for FTAB = 1, FTF = 1
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IDT7381 16-BIT CASCADABLE ALU
COMMERCIAL TEMPERATURE RANGE
D0 L1 D1 L2
IN PU T
Dn OUTPUT
In -- t1-- -- t2--
-- tn--
Figure 8. Propagation Delay = t1 + t2 + . . . + tn N-Cascaded Devices
AC TEST CONDITIONS
Input Rise levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3V 3ns 1.5V 1.5V Figure 1
15
IDT7381 16-BIT CASCADABLE ALU
COMMERCIAL TEMPERATURE RANGE
TEST WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
V CC 7.0V 500 VIN Pulse Generator RT D.U.T. 50pF 500 C
L
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Open Closed Switch
V OUT
DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
SET-UP, HOLD, AND RELEASE TIMES
DATA INPUT tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tH 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
PULSE WIDTH
LOW -HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE 1.5V 1.5V
tSU
tH
PROPAGATION DELAY
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
ENABLE AND DISABLE TIMES
ENABLE DISABLE 3V CONTROL INPUT tPZL OUTPUT NORMALLY LOW SW ITCH CLOSED tPZH OUTPUT NORMALLY HIGH SWITCH OPEN 3.5V 1.5V 0.3V tPHZ 0.3V 1.5V 0V 0V VOH tPLZ 1.5V 0V 3.5V VOL
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
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IDT7381 16-BIT CASCADABLE ALU
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
ID T XXXX Device Type XX Speed X Package
J
Plastic Leaded Chip C arrier (J68-1)
25 30 40 55
Speed Grade
7381L
16-Bit ALU
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for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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